GS_VGA Project Status (08/02/2011 - 03:19:46)
Project File:	GS_VGA.xise	Parser Errors:	No Errors
Module Name:	GS_VGA	Implementation State:	Programming File Generated
Target Device:	xc3s500e-4fg320	Errors:	No Errors
Product Version:	ISE 12.1	Warnings:	No Warnings
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	78	9,312	1%
Number of 4 input LUTs	258	9,312	2%
Number of occupied Slices	155	4,656	3%
Number of Slices containing only related logic	155	155	100%
Number of Slices containing unrelated logic	0	155	0%
Total Number of 4 input LUTs	275	9,312	2%
Number used as logic	256
Number used as a route-thru	17
Number used as Shift registers	2
Number of bonded IOBs	20	232	8%
Number of BUFGMUXs	2	24	8%
Average Fanout of Non-Clock Nets	3.50

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0, Component Switching Limit: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Tue Aug 2 03:19:06 2011	0	0	0
Translation Report	Current	Tue Aug 2 03:19:10 2011	0	0	0
Map Report	Current	Tue Aug 2 03:19:16 2011	0	0	2 Infos (0 new)
Place and Route Report	Current	Tue Aug 2 03:19:36 2011	0	0	0
Power Report
Post-PAR Static Timing Report	Current	Tue Aug 2 03:19:39 2011	0	0	4 Infos (0 new)
Bitgen Report	Current	Tue Aug 2 03:19:44 2011	0	0	0

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Report	Current	Tue Aug 2 03:19:45 2011
WebTalk Log File	Current	Tue Aug 2 03:19:45 2011

Date Generated: 08/02/2011 - 03:19:46