Mouse_Test Project Status
Project File: Mouse2.xise Parser Errors: No Errors
Module Name: Mouse_Test Implementation State: Programming File Generated
Target Device: xc3s500e-4fg320
  • Errors:
No Errors
Product Version:ISE 12.1
  • Warnings:
31 Warnings (14 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 77 9,312 1%  
Number of 4 input LUTs 82 9,312 1%  
Number of occupied Slices 80 4,656 1%  
    Number of Slices containing only related logic 80 80 100%  
    Number of Slices containing unrelated logic 0 80 0%  
Total Number of 4 input LUTs 103 9,312 1%  
    Number used as logic 82      
    Number used as a route-thru 21      
Number of bonded IOBs 11 232 4%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 3.06      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Aug 4 22:24:16 2011031 Warnings (14 new)1 Info (0 new)
Translation ReportCurrentThu Aug 4 22:25:14 2011000
Map ReportCurrentThu Aug 4 22:25:20 2011003 Infos (1 new)
Place and Route ReportCurrentThu Aug 4 22:25:41 2011000
Power Report     
Post-PAR Static Timing ReportCurrentThu Aug 4 22:25:44 2011004 Infos (0 new)
Bitgen ReportCurrentThu Aug 4 22:26:00 2011000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentThu Aug 4 22:26:01 2011
WebTalk Log FileCurrentThu Aug 4 22:26:01 2011

Date Generated: 08/04/2011 - 23:41:54