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See OR1k Architecture document (www.opencores.org) for more information about platform and commands.
target jtag jtag://host:portExample: target jtag jtag://localhost:9999
or1ksim commandor1ksim OpenRISC 1000 Architectural
Simulator, proprietary commands can be executed.
info or1k sprinfo or1k spr groupinfo or1k spr groupnoinfo or1k spr group registerinfo or1k spr registerinfo or1k spr groupno registernoinfo or1k spr registernospr group register valuespr register valuespr groupno registerno valuespr registerno valueSome implementations of OpenRISC 1000 Architecture also have hardware trace. It is very similar to gdb trace, except it does not interfere with normal program execution and is thus much faster. Hardware breakpoints/watchpoint triggers can be set using:
$LEA/$LDATA$SEA/$SDATA$AEA/$ADATA$FETCHWhen triggered, it can capture low level data, like: PC, LSEA,
LDATA, SDATA, READSPR, WRITESPR, INSTR.
hwatch conditionalhwatch ($LEA == my_var) && ($LDATA < 50) || ($SEA == my_var) && ($SDATA >= 50)
hwatch ($LEA == my_var) && ($LDATA < 50) || ($SEA == my_var) && ($SDATA >= 50)
htrace infohtrace trigger conditionalhtrace qualifier conditionalhtrace stop conditionalhtrace record [data]*htrace enablehtrace disablehtrace rewind [filename]If filename is specified, new trace file is made and any newly collected data
will be written there.
htrace print [start [len]]htrace mode continuoushtrace mode suspend